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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. c 03/17/06 is62wv10248bll issi ? copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. 1m x 8 low voltage, ultra low power cmos static ram features ? high-speed access time: 55ns, 70ns ? cmos low power operation: 36 mw (typical) operating 12 w (typical) cmos standby ? ttl compatible interface levels ? single power supply: 2.5v--3.6v v dd (is62wv10248bll) ? fully static operation: no clock or refresh required ? three state outputs ? industrial temperature available ? lead-free available description the issi is62wv10248bll is a high-speed, 8m bit static rams organized as 1m words by 8 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. the is62wv10248bll is packaged in the jedec standard 48-pin mini bga (7.2mm x 8.7mm). functional block diagram march 2006 a0-a19 cs1 oe we 1m x 8 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 cs2
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 03/17/06 is62wv10248bll issi ? pin descriptions a0-a1 9 address inputs cs1 chip enable 1 input cs2 chip enable 2 input oe output enable input we write enable input i/o0-i/o7 input/output nc no connection v dd power gnd ground 48-pin mini bga (b) (7.2mm x 8.7mm) pin configuration 1 2 3 4 5 6 a b c d e f g h nc oe a 0 a 1 a 2 cs2 nc nc a 3 a 4 cs1 nc i/o 0 a 5 a 6 nc i/o 4 gnd i/o 1 a 17 a 7 i/o 5 v dd v dd i/o 2 nc a 16 i/o 6 gnd i/o 3 nc a 14 a 15 nc i/o 7 nc a 12 a 13 we nc a 18 a 8 a 9 a 10 a 11 a 19 nc nc
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. c 03/17/06 is62wv10248bll issi ? dc electrical characteristics (over operating range) symbol parameter test conditions v dd min. max. unit v oh output high voltage i oh = -1 ma 2.5-3.6v 2.2 ? v v ol output low voltage i ol = 2.1 ma 2.5-3.6v ? 0.4 v v ih input high voltage 2.5-3.6v 2.2 v dd + 0.3 v v il (1) input low voltage 2.5-3.6v ?0.2 0.6 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a notes: 1. v il (min.) = ?1.0v for pulse width less than 10 ns. absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.2 to v dd +0.3 v v dd v dd related to gnd ?0.2 to +3.8 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (v dd ) range ambient temperature i s62wv10248bll commercial 0c to +70c 2.5v - 3.6v industrial ?40c to +85c 2.5v - 3.6v truth table mode we we we we we cs1 cs1 cs1 cs1 cs1 cs2 oe oe oe oe oe i/o operation v dd current not selected x h x x high-z i sb 1 , i sb 2 (power-down) x x l x high-z i sb 1 , i sb 2 output disabled h l h h high-z i cc read h l h l d out i cc write l l h x d in i cc
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 03/17/06 is62wv10248bll issi ? ac test loads figure 1 figure 2 capacitance (1) symbol parameter cond itions max. unit c in input capacitance v in = 0v 8 pf c out input/output capacitance v out = 0v 10 pf note: 1. tested initially and after any design or process changes that may affect these parameters. ac test conditions parameter is62wv10248bll (unit) input pulse level 0.4 to v dd -0.3v input rise and fall times 5 ns input and output timing v ref and reference level output load see figures 1 and 2 is62wv10248bll 2.5v - 3.6v r1( ) 102 9 r2( ) 1728 v ref 1.5v v tm 2.8v r1 30 pf including jig and scope r2 output vtm r1 5 pf including jig and scope r2 output vtm
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. c 03/17/06 is62wv10248bll issi ? power supply characteristics (1) (over operating range) is62wv10248bll symbol parameter test conditions max. max. unit 55 70 i cc v dd dynamic operating v dd = max., com. 30 25 ma supply current i out = 0 ma, f = f max ind. 35 30 i cc 1 operating supply v dd = max., cs1 = 0.2v com. 5 5 ma current we = v dd -0.2v ind. 5 5 cs2 = v dd -0.2v, f = 1mhz i sb 1 ttl standby current v dd = max., com. 0.3 0.3 ma (ttl inputs) v in = v ih or v il ind. 0.3 0.3 cs1 = v ih , cs2 = v il , f = 1 mh z i sb 2 cmos standby v dd = max., com. 20 20 a current (cmos inputs) cs1 v dd ? 0.2v, ind. 25 25 cs2 0.2v, typ. (1) 33 v in v dd ? 0.2v, or v in 0.2v , f = 0 note: 1. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 03/17/06 is62wv10248bll issi ? ac waveforms read cycle no. 1 (1,2) (address controlled) ( cs1 = oe = v il , cs2 = we = v ih ) data valid previous data valid t aa t oha t oha t rc d out address read cycle switching characteristics (1) (over operating range) 55 ns 70 ns symbol parameter min. max. min. max. unit t rc read cycle time 55 ? 70 ? ns t aa address access time ? 55 ? 70 ns t oha output hold time 10 ? 10 ? ns t acs1/ t acs2 cs1/ cs2 access time ? 55 ? 70 ns t doe oe access time ? 25 ? 35 ns t hzoe (2) oe to high-z output ? 20 ? 25 ns t lzoe (2) oe to low-z output 5 ? 5 ? ns t hzcs1/ t hzcs2 (2) cs1/ cs2 to high-z output 0 20 0 25 ns t lzcs1/ t lzcs2 (2) cs1/ cs2 to low-z output 10 ? 10 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0.4v to v dd -0.3v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. c 03/17/06 is62wv10248bll issi ? ac waveforms read cycle no. 2 (1,3) ( cs1 , cs2, oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , cs1 = v il . cs2= we =v ih . 3. address is valid prior to or coincident with cs1 low and cs2 high transition. t rc t oha t aa t doe t lzoe t acs1/ t acs2 t lzcs1/ t lzcs2 t hzoe high-z data valid t hzcs address oe cs1 cs2 dout
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 03/17/06 is62wv10248bll issi ? write cycle switching characteristics (1,2) (over operating range) 55 ns 70 ns symbol parameter min. max. min. max. unit t wc write cycle time 55 ? 70 ? ns t scs1/ t scs2 cs1/ cs2 to write end 45 ? 60 ? ns t aw address setup time to write end 45 ? 60 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwe (4) we pulse width 40 ? 50 ? ns t sd data setup to write end 25 ? 30 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 25 ? 25 ns t lzwe (3) we high to low-z output 5 ? 5 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0.4v t o v dd - 0.3v and output loading specified in figure 1. 2. the internal write time is defined by the overlap of cs1 low, cs2 high and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to th e rising or falling edge of the signal that terminates the write . 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 4. t pwe > t hzwe + t sd when oe is low. ac waveforms write cycle no. 1 ( cs1 /cs2 controlled, oe = high or low ) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. c 03/17/06 is62wv10248bll issi ? write cycle no. 2 ( we controlled: oe is high during write cycle) write cycle no. 3 ( we controlled: oe is low during write cycle) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 03/17/06 is62wv10248bll issi ? data retention switching characteristics symbol parameter test condition min. max. unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = 1.2v, cs1 v dd ? 0.2v ? 20 a t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns data retention waveform ( cs1 cs1 cs1 cs1 cs1 controlled) data retention waveform (cs2 controlled) v dd cs1 v dd - 0.2v t sdr t rdr v dr cs1 gnd 3.0v 2.2v data retention mode v dd cs2 0.2v t sdr t rdr v dr 0.4v cs2 gnd 3.0 2.2v data retention mode
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. c 03/17/06 is62wv10248bll issi ? ordering information: is62wv10248bll (2.5v - 3.6v) industrial range: ?40c to +85c speed (ns) order part no. package 55 is62wv10248bll-55bi mini bga (7.2mm x 8.7mm) IS62WV10248BLL-55BLI mini bga (7.2mm x 8.7mm), lead-free 70 is62wv10248bll-70bi mini bga (7.2mm x 8.7mm) 70 is62wv10248bll-70xi die
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 03/17/06 is62wv10248bll issi ? mini ball grid array package code: b (48-pin) notes: 1. controlling dimensions are in millimeters. seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (48x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h mbga - 7.2mm x 8.7mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 ? ? 0.047 a1 0 .24 ? 0.30 0.00 9 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 8.60 8.70 8.80 0.33 9 0.343 0.346 d1 5.25bsc 0.207bsc e 7.10 7.20 7.30 0.280 0.283 0.287 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016

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